Magnetostrictive stability device



Aug- 18, 1954 J. A. PERscHY l I 3,145,369'-.

MAGNETOSTRICTIVE STABILITY DEVICE Filed May 5l, 1962- DECODER ATTORNEYUnited States Patent O 3,l45,39 MAGNETQSTRECTEVE STAMMTY DEVCE James A.Persehy, Silver Spring, Md. (lSdS E. Crestview Drive, Laurel, Md.) FiledMay 3l, 1962, Ser. No. 199,969 3 Claims. (Cl. Mii- 173) This inventionrelates to recirculating memory systems and, more particularly, to animproved stability circuit for a memory system utilizing amagnctostrictive delay line.

A magnetostrictive delay line consists of a nickel wire element, amagnetostrictive write transducer and a magnetostrictive readtransducer. The write transducer is attached to the nickel wire elementby means ol' two metal arms. When a bit of information is written on thenickel `wire element, the write transducer twists the element byrotation of the metal arms in either a clochwise .or counter-clockwisedirection, and then allows the element to return toits neutral position.The torsional impulse travels in both directions from the metal arms. none side of the arms, the impulse is terminated in a way that causes ynorellection. The impulse on the other side of the arms travels down theelement. The impulse is picked up on the other end of the element by theread transducer which is attached to the element in the same manner asthe write transducer. Current pulses into the write transducer 'willproduce output signals from the read transducer, delayed by the soniclength of the wire element. Bits of information ymay be closed-looprecirculated on the magnetostrictive delay line by a read-write,ampliiien The sonic length of a delay line may change because oftemperature and aging effects. The usual delay line is preciselyconstructed to give the exact amount of required delay. As the bit rateincreases the cost of manufacture increases many times to keep theamount of change in sonic length within the maximum value that can betolerated by the memory system. This maximum value of change is usuallycalled the drift time and is expressed as a percentage of a bit time.Normally, a delay line can tolerate a driftV time of less than plus orminus one quarter of a bit. Using the stabilizing approach of theinstant invention a drift time of more than plus or minus onehalf a bitcan be tolerated.

This drift problem is anticipated and is usually avoided as much aspossible by costly yprecise manufacturing methods. The present inventioncan tolerate the increased amount of drift time in its recirculatingacoustic delay line because of an improved gating and retirningtechnique.

To insure the availability of a precise retiming period an improvedpulse generator is utilized. The accuracy of the pulse generator doesnot rest in the accuracy oi its frequency standard but rather in itsassociated circuits. This pulse generator has the ilexibiiity or" beingable to provide the required pulse width over a wide variation offrequency inputs, by dividing the frequency standard by the integralnumber from two to four. The output of the timing generator is a 225nanosecond pulse occurring at the rate of one megacycle, regardless ofinstability of the frequency standard. In order to obtain other outputpulse rates or widths, it would only be necessary to use differentvalues oi delay for the delay lines contained therein.

One object of the present invention,'therefore, resides in the provisionof an improved memory system employingr a magnetostrictive delay lineand a novel stability circuit therefor.

Another object of the invention is to provide a memory circuit employinga novel pulse generator vwhose stability is independent of anyvariations in output of its associated frequency standard.

ice

'A further object of the invention is to provide Van iinproved memorysystem having a low power requirement.

The above-mentioned and `other features and objects of this inventionwill Ybecome more apparent by reference to the following'descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a generalized block diagram of the invention;

FIG. 2 is a block diagram or the pulse generator employed; and

FIG. 3 is a block diagram of a data loop employed.

The memory system, shown in FlG. l, has aV capacity of 2,649 bits. Theblock 1 represents a .decoder portieri a memory system. This squarerepresents the decoder with all of its electronic circuits required tointerpret the incoming `information signal ,and transfer theintelligence contained therein to the proper subsequent intelligencechannels. It is not the purpose of this application to specify the typeof decoder employed, for it may Ivary depending on the environmentwithin which it operates. The only requirement of this circuit is thatit be asource of four signals commonly utilized in memory systems. Thesetour outputs are sequentially operated, the .first initiates a memoryloading sequence vand is applied to two read-Write `amplifiers 2 and 3,to erase any information contained therein, the second yis aconditioning pulse applied to an. inject control 'flip-dop 4, the thirdfurnishes a marker bit to a marker inject and gate 5, and the fourthfurnishes data bits to a data inject and gate 6.

There are two magnetostrictive delay line-loops in the magnetostrictivedelay line memory; a data loop '7 consisting of a data delay line 8 andthe data read-write ampliiierl, and a marker loop 9 consisting of atiming marker delay line lll and the marker read-write amplifier 3. Thelength of the data loop is 2,049 memory clock pulse times, while thelength of the marker loop -9 is 2,048 memory clock pulse times. Sinceboth loops recirculate in synchronization with the output of avpulsegenerator 11,there is a precise timing relationship between the two.During the load process, every time the timing marker appears in themarker loop output and enables a data inject and gate 6, a databitvisinjected into the data loop 7. A data bit Will be inserted into adjacentpositions on the data loop onvevery cycle of the marker. loop until theload process is complete. This completion isr signified by thecoincidence of the timing marker from the marker loopk 9 and thereappearance of the lirsty data bit injected into the data loop 7 yinareset and gate 12. A bit from the data loop 7 isesampled fortransmission inian output gate 13 everyeighth cycle of the timing markerin the 'marker loop, as specied in a'counter circuit 14. The separateblocks illustrated are conventional in Aaccordance with the legendsapplied thereto and therefore need not be shown in detail.

The pulse .generator l1 employed in the instant invention is shown inFIG. 2, wherein a three megacycle oscillator .20, of standard design, isemployed as the frequency standard to drive the subsequent timinggenerator circuitry. lts output pulse width isindependent of anyvariation from-the frequency standard duetto its jitter or drift. Aninput amplifier 22 receives the Vsignal from the-oscillator 2liandtransmits it'to an and gate 2d. This gatehas two inputs, one of whichreceives the signal from theinput amplifier 22, the second of which isan enabling pulse from an or gate inverter 26. In the absence of thisenabling input, the and gate l24 cannot transmit the signal receivedfrom the Vvoscillator to the subsequent circuitry. Such an enablinginput is available when the rst vpulse from the oscillator Ztl issupplied.

The output ot the and gate 24 drives a clock generator ilip-ilop 28 toits iirst stable state wherein it' La applies one of its outputs to aclock inverter 30 and the other to a reset amplifier 32.

The output of the reset amplifier 32 drives a delay line 34, having alength of 225 nano-seconds and a delay line 36, having a length of 425nano-seconds. The output of delay line 34 is applied to an or gate 38 bya line 39. The output of the or gate 38 is applied to the clockgenerator tiip-fiop 28 driving it back to its second stable statewherein it reverses the polarity of its outputs. The resulting pulseapplied to the clock inverter 30 is the timing pulse used throughout thememory circuit, while the corresponding pulse applied to the resetamplifier 32 is used as an inhibitory pulse. The output of the or gate38 is also applied to the or gate inverter 26 which then removes theenabling pulse from the and gate 24 suspending its operation.

The output of day line 36 will begin to drive a delay line 40 having alength of 200 nano-seconds and will be applied to the or gate 38 by aline 41 before the output from the delay line 34 ceases. Although theoutput of the or gate 38 will be applied to the clock generatoriiip-fiop 28, it is of such a nature as to keep that ipop in its secondstable state. The out-put of the or gate 38 will also be applied to theor gate inverter 26 which Will continue to inhibit the and gate 24. Theoutput of the delay line 46 will be applied to the or gate 38 by a line42 before the output from the delay line 36 ceases. The output of the orgate 38 will not affect the clock generator iiip-fiop 28 but willcontinue to inhibit the and gate 24 through the or gate inverter 26. Thetotal inhibiting period for the and gate 24 is 625 nano-seconds, andcauses two positive half cycles of the 3 megacycle input to berepressed. The clock generator flip-hop 28 will be triggered on thefourth positive half cycle to begin the process again.

The output of the clock inverter 30 will be a clock pulse with aduration of 225 nano-seconds and a repetition rate of one megacycle, andwill be applied to both a write pulse amplifier 44 and a read pulseamplifier 46. The output of these amplifiers will provide the requiredtiming pulse throughout the memory circuits, having a given widthregardless of variations in the frequency standard.

In operation, the circuitry associated with the 3 megacycle oscillatoracts as a pulse generator. The pulse width is determined by the delayline 34 and the total blanking time is the sum of the delay lines 36 and40. Therefore, it can be seen that the pulse width can be easily alteredby changing the value of the delay line 34. The value of the combinedblanking time is chosen in order to inhibit the unwanted positivesignals generated by the oscillator which otherwise could affect therepetition rate of the clock pulses generated by the clock generatorhip-flop 28.

Although the combined blanking time is determined by the sum of thedelay lines 36 and 40, these delay lines may not be combined into onefor obvious reasons, that is, an inhibitory eiect from delay line 36must be felt by both the and gate 24 and the clock generator flip-flop2S before the inhibitor effect from delay line 34 ceases.

Referring now to FIG. 3, there may be seen a block diagram of the dataloop 7 employed in the invention. Since both the data loop 7 and themarker loop 9 are identical, the following description is applicable toboth loops when operating in the recirculating mode.

The information circulating in the data delay line 8 will be read by aread transducer 50 as a positive pulse for a one and a negative pulsefor a zero. The signal is amplified and clipped by a read amplifier 52which has a phase split output. When the read amplifier 52 reads a one,its output enables a read phase one and gate 54 while simultaneouslyinhibiting the read phase two and gate 56. When the read amplifier 52reads a zero, the functioning of its output is reversed. Both the readand gate 54 and the read and gate 56 have two inputs, one of which isthe enabling pulse from the read amplifier 52, the other of which is aninhibiting pulse from a read pulse ampliiier inverter 58.

The output of the read and gate 54, signifying the reading of a one inthe read amplifier 52, is applied to a read or gate 60. The or gate 65.)has two inputs, one of which is a recirculating data input from the readand gate 54, and the other is a data insertion input which is usedduring the loading process as described with reference to FIG. l.

The output from the read or gate 60 drives the first stage of a dataflip-iiop 62 to its one position wherein an enabling pulse of positivepolarity is applied to a phase one write and gate 64.

The pulse generator 11 now furnishes a read pulse to the read pulseamplifier 45, and a write pulse to the write pulse amplifier 44. Theamplified read pulse is inverted in the inverter 58 and applied as aninhibiting pulse to both the read and gate 54 and the read and gate 56.During the duration of this read pulse no information may pass throughthe read and gate S4 and the read or gate 60 to trigger the dataflip-ffop 62 which momentarily stores a single bit of data for the duration of the read pulse.

Simultaneous with the application of the read pulse to the read and gate54 as an inhibiting pulse, the write pulse amplifier 44 applies a writepulse to the write and gate 64 and a phase two write and gate 65.

The write Land gate 64 has two inputs, one of which is an enabling datainput from the data fiip-flop 62, and the other is an enabling timingpulse from the write pulse amplifier 44. The data pulse passing throughthe write and gate 64 is of constant amplitude throughout its entireduration, and its duration is determined by the availability of thewrite pulse.

The output from the write and gate 64 is applied to a write amplier 66where the pulse is amplified and then it is applied to a writetransducer 63 which writes the retimed data pulse back into the delayline 8.

When the read amplifier 52 is reading a zero, its output applies anenabling pulse to a read and gate 56 whose output is applied to a reador gate 70 whose output drives the second stage of the data ilipflop 62to its zero position wherein an enabling pulse is applied to the writeand gate 65. On the next application of the simultaneous read pulse andwrite pulse, the read pulse inhibits the operation of both the read andgate 54 and the read and gate 56, isolating the data flip-fiop 62 fromthe read amplifier 52. With the data flip-flop 62 again isolated, itsoutput will remain constant during the entire write pulse from the writepulse amplier 44, enabling the Write and gate 72, whose output isamplified in a write amplifier 74 and applied to the data delay line 8by the write transducer 63.

In operation, the data flip-flop 62 is triggered by the read and gate 54and the read and gate 56 depending on whether a zero or a one has beenread by the read transducer 5t). Previously in systems of this nature,no attempt was made to isolate the data which was about to be resarnpledand retimed and inserted back into the delay line. The read pulseapplied as an inhibiting pulse to the gates 54 and 56 isolates thestorage facility, the data flip-flop 62, during the entire resamplingand retiming period. This means that the retimed pulse is not degradedby jitter in the delay line. This novel isolation arrangement enablesthe recirculating memory system to tolerate a larger amount of drifttime than was previously possible.

While i have described above the principles of my invention inconnection with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationto the scope of my invention as set forth in the objects thereof and inthe accompanying claims.

I claim:

1. In a recirculating memory system of the type employing amagnetostrictive delay line for storing a plurality of data bits, a readtransducer, and a write transducer, a stability device therefore,comprising, means for generating basic timing signals, each of saidsignals having an enabling period and an inhibiting period, an inverterconnected to said timing means for generating an inverted timing signalhaving an inhibiting period corresponding to said enabling period ofsaid basic timing signal and an enabling period corresponding to saidinhibiting period of said basic timing signal, means for storingsuccessive data bits during said enabling period of said basic timingsignal and said corresponding inhibiting period of said inverted timingsignal, a iirst gating means responsive to said read transducer and saidinverter for passing data bits to said storing means during the enablingperiod of said inverted timing signal, and a second gating meansresponsive to said storing means and said generating means for removingthe input to said write transducer from said storing means during theinhibiting period of said basic timing signal, whereby said writetransducer rewrites the retimed data bit into said delay line.

2. In a recirculating memory system of the type employing amagnetostrictive delay line for storing a plurality of data bits, a readtransducer, and a write transducer, a stability device therefore,comprising, means for generating basic timing signals, each of saidsignals having an enabling period and an inhibiting period, saidenabling period being shorter in time than each of said data bits, aninverter connected to said timing means for generating an invertedtiming signal having an inhibiting period corresponding to said enablingperiod of said basic timing signal and an enabling period correspondingto said inhibiting period of said basic timing signal, a first and gateconnected to said read transducer and said inverter for passingtherethrough one of said data bits for the duration of the enablingperiod of said inverted timing signal, a multivibrator responsive tosaid irst and gate for storing said passed data bit for the duration ofthe inhibiting period of said inverted timing signal, a second and gateresponsive to said multivibrator and said generating means for passingsaid stored data bit to said write transducer for the duration of saidenabling period of said basic timing pulse, whereby said stored data bitis retimed and said write transducer reinserts said data bit into saiddelay line.

3. In a recirculating memory system of the type employing amagnetostrictive delay line for storing a plurality of positive andnegative data bits, a read transducer, and a write transducer, astability device therefore, comprising, means for continuouslygenerating basic timing signals having an enabling time period shorterthan one of said data bits and an inhibiting time period for theremainder of each timing period, an inverter circuit connected to saidtiming means for generating an inverted timing signal having aninhibiting period corresponding to said enabling period of said basictiming period and an enabling period corresponding to said inhibitingperiod of said basic timing period, an amplifier responsive to said readtransducer for producing a positive and a negative output signal foreach of said recirculating data bits, a multivibrator having a firststage and a second stage for storing said positive signals from saidamplifier, a irst, phase one and gate connected to said ampliiier andsaid inverter for passing said positive output signal corresponding toIsaid positive data bits during said enabling period of said invertedtiming signal to said iirst stage of said multivibrator and for removingthe input to said rst stage during the inhibiting period of saidinverted timing signal, a first, phase two and gate connected to saidamplier and to said inverter for passing said positive output signalcorresponding to said negative data bit during the enabling period ofsaid inverted timing signal to said second stage of said multivibratorand for removing the input to said second stage during the inhibitingperiod of said inverted timing signal, a second, phase one and gateconnected to said Iirst stage of said multivibrator and to said basictiming source for sampling the contents of said iirst stage of saidmultivibrator during the enabling time4 period of said basic timingsignals and for removing the output of said first stage from said writetransducer during said isolating period of said basic timing signal, anda second, phase two and gate connected to said second stage of saidmultivibrator and to said basic timing source for sampling the contentsof said second stage during the enabling time period of said basictiming signals and for isolating said write transducer from said secondstage during said inhibiting period of said basic timing signals,whereby each of said recirculating data bits in said delay line isretimed by said enabling portion of said basic timing signals andreinserted into said delay line by said write transducer.

References Cited in the le of this patent UNITED STATES PATENTS2,933,717 Tyas Apr. 19, 1960 2,961,535 Lanning Nov. 22, 1960 `2,978,680Schulte Apr. 4, 1961 3,021,484 Mestre Feb. 13, 1962

1. IN A RECIRCULATING MEMORY SYSTEM OF THE TYPE EMPLOYING AMAGNETOSTRICTIVE DELAY LINE FOR STORING A PLURALITY OF DATA BITS, A READTRANSDUCER, AND A WRITE TRANSDUCER, A STABILITY DEVICE THEREFORE,COMPRISING, MEANS FOR GENERATING BASIC TIMING SIGNALS, EACH OF SAIDSIGNALS HAVING AN ENABLING PERIOD AND AN INHIBITING PERIOD, AN INVERTERCONNECTED TO SAID TIMING MEANS FOR GENERATING AN INVERTED TIMING SIGNALHAVING AN INHIBITING PERIOD CORRESPONDING TO SAID ENABLING PERIOD OFSAID BASIC TIMING SIGNAL AND AN ENABLING PERIOD CORRESPONDING TO SAIDINHIBITING PERIOD OF SAID BASIC TIMING SIGNAL, MEANS FOR STORINGSUCCESSIVE DATA BITS DURING SAID ENABLING PERIOD OF SAID BASIC TIMINGSIGNAL AND SAID CORRESPONDING INHIBITING PERIOD OF SAID INVERTED TIMINGSIGNAL, A FIRST GATING MEANS RESPONSIVE TO SAID READ TRANSDUCER AND SAIDINVERTER FOR PASSING DATA BITS TO SAID STORING MEANS DURING THE ENABLINGPERIOD OF SAID INVERTED TIMING SIGNAL, AND A SECOND GATING MEANSRESPONSIVE TO SAID STORING MEANS AND SAID GENERATING MEANS FOR REMOVINGTHE INPUT TO SAID WRITE TRANSDUCER FROM SAID STORING MEANS DURING THEINHIBITING PERIOD OF SAID BASIC TIMING SIGNAL, WHEREBY SAID WRITETRANSDUCER REWRITES THE RETIMED DATA BIT INTO SAID DELAY LINE.